20.500.12556/RUL-170331 FRI-V: RISC-V CPE na vezju FPGA FRI-V: RISC-V CPU on an FPGA circuit V zadnjih letih, še posebej na področju vgrajenih sistemov, popularnost pridobiva odprta ukazna arhitekrura RISC-V. Razvita je bila na Univerzi Berkeley, s poudarkom na modularnosti in prilagodljivosti, ki je uporabna ne samo za akademske, temveč tudi za komercialne potrebe. Na tej osnovi smo implementirali preprost cevovoden procesor FRI-V s programirljivim logičnim vezjem FPGA, ki podpira osnovni RV32I ukazni nabor skupaj z razširitvijo za privilegirane ukaze ZICSR in razširitvijo M za celoštevilsko množenje in deljenje. Procesorju smo dodali še predpomnilnike, podporo za pasti ter glavni pomnilnik DDR2. Za komunikacijo med CPE in vhodno izhodnimi enotami smo implementirali podatkovno vodilo, ki temelji na odprtem standardu Wishbone. Kodo za procesor smo napisali v jeziku SystemVerilog in ga sintetizirali za ploščo Nexys A7 50T. Pravilnost delovanja procesorja smo preverjali s kombinacijo formalne verifikacije, simulacij in izvajanja programov na končnem procesorju. Za oceno zmogljivosti končne različice procesorja FRI-V smo uporabili test CoreMark v katerem je dobil oceno 2.28 CoreMarka na MHz. To ga po zmogljivosti postavlja v bližino mikrokrmilnikov kot sta Renesas RX610 in STM32F051C8 (32-bitni ARM Cortex M0). In recent years, especially in the field of embedded systems, the open instruction architecture RISC-V has been gaining popularity. It was developed at the University of Berkeley, with an emphasis on modularity and flexibility, which is useful not only for academic but also for commercial needs. On this basis, we implemented a simple pipelined processor FRI-V with a programmable logic circuit FPGA, which supports the basic RV32I instruction set along with the extension for privileged instructions ZICSR and the extension M for integer multiplication and division. We added caches, support for traps and DDR2 main memory to the processor. For communication between the CPU and input/output units, we implemented a data bus based on the open standard Wishbone. The code for the processor was written in the SystemVerilog language and synthesized for the Nexys A7 50T board. The correctness of the processor operation was verified by a combination of formal verification, simulations and program execution on the final processor. To evaluate the performance of the final version of the FRI-V processor, we used the CoreMark test, in which it received a score of 2.28 CoreMark per MHz. That score puts it in the vicinity of microcontrollers such as Renesas RX610 and STM32F051C8 (32-bit ARM Cortex M0). FPGA RISC-V Wishbone DDR2 FRI-V mikrokrmilnik FPGA RISC-V Wishbone DDR2 FRI-V microcontroller true false false Slovenski jezik Angleški jezik Diplomsko delo/naloga 2025-07-03 15:34:16 2025-07-03 15:34:19 2025-07-04 08:09:24 0000-00-00 00:00:00 2025 0 0 0000-00-00 NiDoloceno NiDoloceno NiDoloceno 0000-00-00 0000-00-00 0000-00-00 38309 241367043 Jelovcan_Jakob_-_FRI-V_RISC-V_CPE_na_vezju_FPGA.pdf Jelovcan_Jakob_-_FRI-V_RISC-V_CPE_na_vezju_FPGA.pdf 1 69048F0BCCC46BFBCC8C798E52733021 09f3453ef7b6d5ea58d950c76fe011346fdcdd26636bec0e599fb5582229ae6c 8530f909-5810-11f0-b232-0050569b8976 https://repozitorij.uni-lj.si/Dokument.php?lang=slv&id=212325 Fakulteta za računalništvo in informatiko 0 0 0