20.500.12556/RUL-120151 A binary neural network on an FPGA Binarna nevronska mreža na programirljivem vezju FPGA In recent years, the performance of convolutional neural networks has been increasing rapidly. But higher performance brings higher computational and memory costs. Research has shown that good accuracy can be achieved even when operands are constrained to only one or two bits. The purpose of this work is to implement a binary neural network with operands constrained to one bit on a field-programmable gate array. The computations in binary neural networks are mostly binary, while the weights require very little memory, making them ideal for hardware implementation. The implemented network was tested on MIO-TCD database, while the implementation was mostly focused on resource consumption and speed. V zadnjih letih se zmogljivosti konvolucijskih nevronskih mrež neprestano povečujejo. Vendar pa se z zmogljivostjo povečuje tudi kompleksnost mrež in s tem poraba računskih virov in virov za shranjevanje uteži. Raziskave so pokazale, da je pri mnogih problemih zadovoljivo delovanje nevronskih mrež doseženo tudi z le enobitnimi ali dvobitnimi operandi. V tem delu smo binarno konvolucijsko mrežo implementirali na reprogramirljivem vezju FPGA. Računske operacije v binarnih mrežah so večinoma binarne, za shranjevanje uteži pa se potrebuje malo prostora, kar jih naredi idealne za implementacijo v strojni opremi. Implementirano mrežo smo testirali na bazi slik MIO-TCD, pri imlementaciji pa smo bili pozorni predvsem na porabo virov in hitrost izvedbe. binary neural network FPGA Verilog ZedBoard binarna nevronska mreža FPGA Verilog ZedBoard true false false Angleški jezik Slovenski jezik Diplomsko delo/naloga 2020-09-16 11:20:08 2020-09-16 11:20:11 2024-02-16 09:12:01 0000-00-00 00:00:00 2020 0 0 0000-00-00 NiDoloceno NiDoloceno NiDoloceno 0000-00-00 0000-00-00 0000-00-00 26804 32142083 Langerholc_Klara_-_Binarna_nevronska_mreza_na_programirljivem_vezju_FPGA.pdf Langerholc_Klara_-_Binarna_nevronska_mreza_na_programirljivem_vezju_FPGA.pdf 1 8E309D43E45A0DF15EA6AFE338D93284 7487b728273d9520a54182988441a2562b41d7aed136c8b280af9b48609b5a80 02e2adeb-a1ba-11eb-a523-00155dcfd717 https://repozitorij.uni-lj.si/Dokument.php?lang=slv&id=134922 Fakulteta za računalništvo in informatiko 0 0 0