20.500.12556/RUL-102973 Numerično modeliranje in simulacija enoelektronskih logičnih vezij Numerical modelling and simulation of single-electron logic circuits V tem delu smo predstavili uporabo orodja MOSES (Monte-Carlo Single- Electronics Simulator), kot metodo za simulacijo komplementarnih enoelektronskih vezij na podlagi ortodoksne teorije. Izvedli smo simulacijo enoelektronske škatle, enoelektronskega tranzistorja in komplementarnega enoelektronskega inverterja. Njihove karakteristike smo ovrednotili pri različnih temperaturah in ocenili njihov potencial za delovanje pri sobni temperaturi. Karakteristike smo primerjali tudi z meritvami realnih struktur, ki so jih izvedli na drugih inštitucijah in ocenili možne razloge za razlikovanje rezultatov. Ocenili smo možnost zamenjave konvencionalnih CMOS vezji z enoelektronsko logiko stanj napetosti in predlagali poenostavljeno strukturo, ki naj bi delovala pri sobni temperaturi. In our contribution we present the use of MOSES (Monte-Carlo Single- Electronics Simulator) as a method for simulation of complementary SET logic circuits based on the orthodox theory. Simulation of single-electron devices including a single-electron box, a single-electron transistor and a complementary single-electron inverter was carried out. Their characteristics were evaluated at different temperatures and the potential for room-temperature operation was assessed. The characteristics were also compared to the measurements obtained at other institutions and deviations between the two were examined. The potential for voltage-state logic to replace conventional CMOS logic circuits was examined and a proposal of a potential structure, operational at room-temperature, was made. enoelektronska logična vezja enoelektronski tranzistor Monte-Carlo. simulacija MOSES logika stanj napetosti single-electron logic circuits single-electron transistor Monte-Carlo MOSES voltage-state logic true false false Slovenski jezik Angleški jezik Magistrsko delo/naloga 2018-09-12 13:10:08 2018-09-12 13:10:11 2022-08-16 03:39:13 0000-00-00 00:00:00 2018 0 0 0000-00-00 NiDoloceno NiDoloceno NiDoloceno 0000-00-00 0000-00-00 0000-00-00 1970-01-01 43741 Kikelj_Miha_-_Numericno_modeliranje_in_simulacija_enoelektronskih_logicnih_vezij.pdf Kikelj_Miha_-_Numericno_modeliranje_in_simulacija_enoelektronskih_logicnih_vezij.pdf 1 AABEC335595D65C7925F87637BCE56F0 452a0f927e1a7eb0032aae2793a001b7f9e78c5dbb92709d2b343eec618ea7f5 ac9b2fef-a1b5-11eb-a523-00155dcfd717 https://repozitorij.uni-lj.si/Dokument.php?lang=slv&id=113349 Fakulteta za elektrotehniko 0 0 0