Off-Chip PDN Modelling and Analysis of Vertical Power Delivery Networks for Logic on Memory ArchitecturesSEČKO, ALJAŽ (Avtor) Strle, Drago (Mentor) Venugopal, Priya (Komentor) power delivery network (PDN)3D heterogeneous integrationLogic on Memory (LoM)IR dropimpedance characterizationTSVhybrid bondingSPICESpectrePythonsimulation framework3D heterogeneous integration is becoming one of the key emerging technologies for next generation high performance computing systems. It has emerged as a response to the continuous need to reduce system dimensions while increasing integration density and system performance. Technologies such as through silicon vias (TSVs) and hybrid bonding enable significantly higher interconnect densities, shorter communication paths, improved bandwidth and energy efficiency compared to conventional 2D and 2.5D integration approaches. However, these benefits also come with new power delivery challenges, as higher integration density leads to increasing current demand, higher power density and reduced voltage margins. As a result, the design of Power Delivery Networks (PDNs) becomes increasingly critical for maintaining power integrity. One of the main motivations behind this work is the development of a simulation environment that supports system technology co-optimization (STCO) by identifying important PDN related design constraints during early design exploration before proceeding to more detailed physical design. The framework addresses this need, as conventional commercial tools are generally less suitable for rapid exploration involving changes to the structure itself. It enables fast parametrization, automatic structure generation and shorter simulation times, making it feasible to evaluate a larger number of design configurations. The objective of this thesis is the development of a scalable, modular and configurable simulation framework for modelling and analysis of PDNs in heterogeneous 3D integrated systems, targeting the Logic on Memory architecture. Particular focus is placed on the off-chip interconnects that deliver power through the 3D stack. The framework is implemented in Python and enables fast generation of SPICE netlists, which are then simulated using the Spectre circuit simulator. It supports both dc operating point analysis for IR drop evaluation and ac analysis for impedance characterization. The off-chip interconnect models use realistic electrical parameters for TSVs, hybrid bonds and microbumps from a manufacturable interconnect set provided by imec. Interconnect models can be selected from the included database or defined using custom RLC values. The on-chip PDN is generated using BEOL metal stack parameters from imec's pathfinding n2 and a14 process technology, with support for frontside PDN (FSPDN) and backside PDN (BSPDN) configurations. The framework enables systematic variation of key design parameters related to geometry, technology parameters, load distribution, TSV connection arrangement and interconnects. In this work, representative case studies of Logic on Memory structures are analysed using the developed framework. The analysis investigates how PDN performance depends on key design parameters, including the number of stacked memory chiplets, the off-chip TSV connection arrangement, standard cell capacitance density and logic chiplet area. Their influence on IR drop and impedance behaviour is evaluated to identify the main parameters limiting PDN performance and the resulting design tradeoffs.20262026-09-08 13:55:01Magistrsko delo/naloga187041VisID: 63328sl