Analysis of a segmented 16-bit resistive digital-to-analog converterZoranović, Jelena (Avtor) Žemva, Andrej (Mentor) Digital-to-Analog converterKelvin–Varley DACdifferential nonlinearityintegral nonlinearityextrapolated reconstruction with interpolation (ER + I)Cadence VirtuosoDigital-to-analog converters (DACs) are fundamental components in modern electronic systems, particularly in high-performance communication and signal processing applications. As resolution increases, DAC architectures become significantly more complex, placing greater demands on accurate simulation, verification, and performance evaluation. A critical aspect of DAC characterization is linearity analysis, defined by differential nonlinearity (DNL) and integral nonlinearity (INL). Conventional evaluation relies on exhaustive sweeping of all input codes, which becomes computationally prohibitive for high-resolution DACs. This challenge is further amplified in Monte Carlo and corner analyses, where the number of required simulations increases dramatically. This thesis presents a comprehensive analysis of a 16-bit segmented resistive Kelvin–Varley DAC implemented and evaluated in the Cadence Virtuoso environment. A structured methodology is developed, covering the complete design flow, from specification and schematic design, illustrated through block diagrams, to simulation setup, performance evaluation, and layout considerations. DC, transient, and noise analyses are performed using carefully defined measurement statements, followed by statistical verification through Monte Carlo and corner analyses. Additionally, the design is compared across two semiconductor technologies: a larger, obsolete technology node in one foundry and a smaller node in another foundry. The performance of different Cadence Spectre simulation engines is investigated with emphasis on the trade-off between simulation speed and accuracy. Furthermore, various tolerance settings were evaluated to assess their impact on the simulation results. Optimization of the Spectre APS simulator, including the use of the conservative aps++ mode with multithreading, enables simulation speeds comparable to Spectre X (CX) while maintaining numerical accuracy. The main contribution of this work is the implementation and adaptation of the Extrapolated Reconstruction with Interpolation (ER + I) method for efficient linearity evaluation. Unlike the conventional approach, which requires the evaluation of all 2n input codes, the proposed method significantly reduces the number of simulated points while preserving accuracy. This results in a substantial reduction in simulation time and computational complexity, making the method particularly suitable for high-resolution DAC analysis. The presented approach provides an efficient and scalable framework for DAC verification and can be extended to a wide range of DAC architectures, with methods adapted to the specific characteristics of each architecture. J. Zoranović20262026-06-12 11:40:03Magistrsko delo/naloga183409UDK: 621.38(043.3)VisID: 63350COBISS_ID: 282464259sl