Towards smaller single-point failure-resilient analog circuits by use of a genetic algorithmRojec, Žiga (Avtor) analog circuitsanalog circuit synthesiscircuit optimizationfailure-resiliencecircuit robustnessFailure-resilient analog circuits are difficult to design, but artificial intelligence can help crawl the topology solution space. Us-ing evolutionary computation-based topology synthesis we evolve analog arcus tangent computational circuits, resilient to any rectifying diode or resistor high-impedance single failure or removal. We encode analog circuit topologies as individuals with an upper-triangular incident matrix. Circuits are evolved using a combined technique utilizing parts of NSGA-II and PSADE, based on a special three-dimensional robustness function. We show that topology size for a failure-resilient circuit can be classes smaller than hand-made component-redundancy-based solutions. Our best failure-resilient topology comprises six diodes, three resistors, and a voltage offset source.20232024-07-23 14:59:17Članek v reviji159756UDK: 621.3.049.7ISSN pri članku: 0352-9045DOI: 10.33180/InfMIDEM2023.205COBISS_ID: 192963843sl