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<metadata xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/"><dc:title>A binary neural network on an FPGA</dc:title><dc:creator>LANGERHOLC,	KLARA	(Avtor)
	</dc:creator><dc:creator>Lotrič,	Uroš	(Mentor)
	</dc:creator><dc:creator>Seog Han,	Dong	(Komentor)
	</dc:creator><dc:subject>binary neural network</dc:subject><dc:subject>FPGA</dc:subject><dc:subject>Verilog</dc:subject><dc:subject>ZedBoard</dc:subject><dc:description>In recent years, the performance of convolutional neural networks has been increasing rapidly. But higher performance brings higher computational and memory costs. Research has shown that good accuracy can be achieved even when operands are constrained to only one or two bits. The purpose of this work is to implement a binary neural network with operands constrained to one bit on a field-programmable gate array. The computations in binary neural networks are mostly binary, while the weights require very little memory, making them ideal for hardware implementation. The implemented network was tested on MIO-TCD database, while the implementation was mostly focused on resource consumption and speed.</dc:description><dc:date>2020</dc:date><dc:date>2020-09-16 11:20:08</dc:date><dc:type>Diplomsko delo/naloga</dc:type><dc:identifier>120151</dc:identifier><dc:identifier>VisID: 26804</dc:identifier><dc:identifier>COBISS_ID: 32142083</dc:identifier><dc:language>sl</dc:language></metadata>
