Hardware implementation of Falcon post-quantum signature schemeSmole, Vid (Avtor) Pilipović, Ratko (Mentor) Sinha Roy, Sujoy (Komentor) Aikata, Aikata (Komentor) Falconpost-quantum cryptographydigital signatureFPGAlattice-based cryptographySystemVerilogQuantum computers threaten to break current signature algorithms, prompting NIST to standardize multiple post-quantum signature algorithms, including Falcon. Falcon's reliance on floating-point arithmetic and recursive algorithms makes designing efficient hardware implementations difficult. This thesis presents the first unified accelerator for signature generation and signature verification for Falcon-512 and Falcon-1024 completely in hardware. Synthesized for Zynq UltraScale+, the design uses 74k LUTs, 38k flip-flops and 175 DSPs, requiring 190k/383k cycles for signature generation and 7.8k/16.6k cycles for verification. Compared to existing partial implementations, our accelerator achieves lower resource utilization while supporting both operations, and with all source code publicly available.20252025-11-14 10:55:02Magistrsko delo/naloga175963sl