<?xml version="1.0"?>
<rdf:RDF xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:dc="http://purl.org/dc/elements/1.1/"><rdf:Description rdf:about="https://repozitorij.uni-lj.si/IzpisGradiva.php?id=165256"><dc:title>Free software support for compact modelling with Verilog-A</dc:title><dc:creator>Bürmen,	Arpad	(Avtor)
	</dc:creator><dc:creator>Tuma,	Tadej	(Avtor)
	</dc:creator><dc:creator>Fajfar,	Iztok	(Avtor)
	</dc:creator><dc:creator>Puhan,	Janez	(Avtor)
	</dc:creator><dc:creator>Rojec,	Žiga	(Avtor)
	</dc:creator><dc:creator>Kunaver,	Matevž	(Avtor)
	</dc:creator><dc:creator>Tomažič,	Sašo	(Avtor)
	</dc:creator><dc:subject>hardware description langugage</dc:subject><dc:subject>Verilog-A</dc:subject><dc:subject>analog circuits</dc:subject><dc:subject>circuit simulation</dc:subject><dc:subject>compact models</dc:subject><dc:description>Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and Free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted.</dc:description><dc:date>2024</dc:date><dc:date>2024-11-28 09:04:58</dc:date><dc:type>Članek v reviji</dc:type><dc:identifier>165256</dc:identifier><dc:language>sl</dc:language></rdf:Description></rdf:RDF>
