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<rdf:RDF xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:dc="http://purl.org/dc/elements/1.1/"><rdf:Description rdf:about="https://repozitorij.uni-lj.si/IzpisGradiva.php?id=136747"><dc:title>Evolutionary synthesis of failure-resilient analog circuits</dc:title><dc:creator>Rojec,	Žiga	(Avtor)
	</dc:creator><dc:creator>Fajfar,	Iztok	(Avtor)
	</dc:creator><dc:creator>Bürmen,	Arpad	(Avtor)
	</dc:creator><dc:subject>evolutionary algorithms</dc:subject><dc:subject>analog circuit synthesis</dc:subject><dc:subject>failure-resilient circuits</dc:subject><dc:subject>NSGA-II algorithm</dc:subject><dc:description>Analog circuit design requires large amounts of human knowledge. A special case of circuit design is the synthesis of robust and failure-resilient electronics. Evolutionary algorithms can aid designers in exploring topologies with new properties. Here, we show how to encode a circuit topology with an upper-triangular incident matrix and use the NSGA-II algorithm to find computational circuits that are robust to component failure. Techniques for robustness evaluation and evolutionary algorithm guidances are described. As a result, we evolve square root and natural logarithm computational circuits that are robust to high-impedance or short-circuit malfunction of an arbitrary rectifying diode. We confirm the simulation results by hardware circuit implementation and measurements. We think that our research will inspire further searches for failure-resilient topologies.</dc:description><dc:date>2022</dc:date><dc:date>2022-05-19 10:08:45</dc:date><dc:type>Članek v reviji</dc:type><dc:identifier>136747</dc:identifier><dc:language>sl</dc:language></rdf:Description></rdf:RDF>
