Implementacija in verifikacija stisnjene (C) razširitve na jedru RISC-V

Pariš, Tadej (avtor), Pilipović, Ratko (mentor), Vreča, Jure (komentor)

Odprtokodna arhitektura nabora ukazov RISC-V je postala priljubljena izbira zaradi zmogljivosti, vsestranske uporabnosti, enostavne implementacije in razširljivosti. Ukazi v osnovni arhitekturi so v RISC slogu vsi enake velikosti, razširitev C pa uvaja stisnjene ukaze kot alternativo pogosto uporabljanim ukazom v osnovni arhitekturi, kar je zelo koristno pri povečanju gostote kode. Implementacija razširitve prinaša svojevrstne izzive: v sistemu s to razširitvijo se v programu in s tem v ukaznem pomnilniku pojavijo stisnjeni in nestisnjeni ukazi, kar pomeni, da ukazi v pomnilniku niso več poravnani na 32 bitov. V zasnovi moramo odstraniti domneve o poravnanosti in prilagoditi mehanizem prevzemanja ukazov na prepletanje ukazov različnih dolžin. RVJ1 je odprtokodno jedro RISC-V z zaporednim izvajanjem ukazov, ki implementira petstopenjski cevovod. Napisano je v jeziku SystemVerilog. V diplomskem delu je predstavljena implementacija stisnjene razširitve (C) na jedru RVJ1 in verifikacija te zasnove. Prevzemno stopnjo jedra smo prilagodili za uporabo s stisnjenimi ukazi z uporabo FIFO vrste za pomnjenje prevzetih podatkov ter kombinacijskega modula za razširitev stisnjenih ukazov v 32-bitne oblike. Zasnovo smo verificirali z uporabo simulacije (s pomočjo odprtokodnih programskih orodij na osnovi jezika Python) in RISC-V arhitekturnih testov. Po verifikaciji smo opravili sintezo zasnove in primerjalne teste ter rezultate analizirali. Pričakovano smo opazili, da se je površina jedra povečala, ugotovili pa smo tudi, da pri novi zasnovi ne pride do znatnega poslabšanja kritične poti. Poleg tega je pri primerjalnem preizkusu Coremark nova zasnova dosegla nekoliko boljši rezultat kot prvotna.

• Jezik: Slovenski jezik
• Ključne besede: RISC-V, razširitev, stisnjeni ukazi
• Vrsta gradiva: Diplomsko delo/naloga
• Organizacija: FRI - Fakulteta za računalništvo in informatiko
• Leto izida: 2026
• PID: 20.500.12556/RUL-187594
• Datum objave v RUL: 11.09.2026

Sekundarni jezik

• Jezik: Angleški jezik
• Naslov: Implementation and Verification of the Compressed (C) Extension on a RISC-V Core

Izvleček

The open-source RISC-V instruction set architecture has become a popular choice due to its performance, versatility, ease of implementation and extensibility. The instructions in the base architecture are, in the RISC fashion, all of uniform size. The C extension introduces compressed instructions as alternatives to frequently used instructions in the base architecture, which is useful for improving code density. Implementing the extensions brings its own challenges: in a system implementing the C extension, programs contain both compressed and non-compressed instructions. This means that instructions are no longer 32-bit aligned in instruction memory. We must remove all assumptions regarding alignment in our design, and we must adapt the instruction fetch mechanism to handle intermixed instructions of variable length. RVJ1 is an open-source in-order RISC-V core that implements a five-stage pipeline. It is written in the SystemVerilog language. In this thesis, we present the implementation of the C extension on the RVJ1 core and the verification of this design. The instruction fetch unit has been adapted to handle compressed instructions, using a FIFO queue to buffer fetched data and a combinational module to expand the compressed instructions into their base 32-bit forms. The design has been verified via simulation (utilising open-source Python-based tools) and the RISC-V architectural test suite. After verifying the design, we performed synthesis and benchmarking, and analysed the results. As expected, the size of the core has increased. The critical path, however, experienced no significant negative change. We also observed that the Coremark benchmark produced a somewhat better score for the new design.

• Ključne besede: RISC-V, extension, compressed instructions